(1) Field of the Invention
The present invention relates to the field of interfaces. More specifically, the present invention relates to high speed interfaces.
(2) Description of Related Art
High speed interfaces handle signals transmitted at very high data rates. Such signals may incur a considerable time delay when transmitted through data paths of different lengths, particularly in high speed interfaces when a small difference in the length of data paths may cause substantial delay between signals transmitted at high data rates. For example, a 4-inch difference between two data paths carrying the same signal can cause approximately one nanosecond delay in arrival time of the signals. Typically, a PC board introduces a delay of approximately 250 picoseconds per inch of signal trace.
Additionally, high speed interfaces include heavy duty output buffers that may cause significant signal delays due to their large size driver transistors. Such transistors may introduce significant delays when signals transition from a high logic level to a low logic level and vice versa. Typically, the delay introduced by an output buffer when a data signal transitions from high to low is different than when the same signal transitions from low to high. Consequently, when a data signal and a corresponding 180.degree. dephased version are driven by an output buffer, a delay between these signals may ensue such that they do not arrive at a sample point at the same time.
FIG. 1 diagrammatically illustrates a DATA signal 102, a DATA signal 104 dephased 180.degree. relative to the DATA signal 102, and a strobe (STB) signal 106 sampling signals 102 and 104. These signals are driven by an output buffer of a high speed interface circuit. In this example, the DATA and DATA signals are sampled when the STB signal 106 transitions from low to high (rising edge). DATA signal 102 and DATA signal 104 are strobed by the rising edge 108 of the STB signal 106 at a median part 116 (shown in dotted line) of a window 114 created by the DATA and DATA signals. In high speed interfaces, the window 114 has a width 110 that becomes smaller and smaller as the rate at which signals 102 and 104 are transmitted (i.e., the data rate) increases. As width 110 decreases, the likelihood that data is inaccurately strobed at the arrival point becomes higher. For example, assuming that an output buffer (not shown) causes delay 118 in the DATA signal transitioning from high to low, rising edge 108 of STB signal 106 may sample the DATA signal 104 at a time when it is not stable (i.e., it is transitioning), thereby causing confusion as to its logic state at its destination. Additionally, signals DATA and DATA arrive at a sample point at slightly different times. This is referred to herein as signal delay mismatch.
It is desirable to provide an apparatus and method for reducing signal delay mismatch in high speed interfaces thereby providing more accurate data transmission through such interfaces.